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MAX2870
23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer/VCO
Table 5. Register 1 (Address: 001, Default: 2000FFF9 HEX ) (continued)
BIT LOCATION
BIT ID
NAME
DEFINITION
Fractional modulus value used to program f VCO . See the Int, Frac, Mod,
and R Counter Relationship section. Double buffered by register 0.
14:3
M[11:0]
Modulus Value
(M)
000000000000 = Unused
000000000001 = Unused
000000000010 = 2
-----
111111111111 = 4095
2:0
ADDR[2:0]
Address Bits
Register address bits
Table 6. Register 2 (Address: 010, Default: 00004042 HEX )
BIT LOCATION
31
BIT ID
LDS
NAME
Lock-Detect
Speed
DEFINITION
Lock-detect speed adjustment.
0 = f PFD P 32MHz
1 = f PFD > 32MHz
Sets noise mode (See the Low-Spur Mode section.)
30:29
SDN[1:0]
Frac-N Noise
Mode
00 = Low-noise mode
01 = Reserved
10 = Low-spur mode 1
11 = Low-spur mode 2
Sets MUX_OUT pin configuration (MSB bit located register 05).
0000 = Three-state output
0001 = D_VDD
0010 = D_GND
28:26
MUX[3:0]
MUX_OUT
Configuration
0011 = R-divider output
0100 = N-divider output/2
0101 = Analog lock detect
0110 = Digital lock detect
0111:1011 = Reserved
1100 = Read register 06 MUX_OUT is configured as serial data out.
1101:1111 = Reserved
25
24
DBR
RDIV2
Reference
Doubler Mode
Reference Div2
Mode
Sets reference doubler mode.
0 = Disable reference doubler
1 = Enable reference doubler
Sets reference divider mode.
0 = Disable reference divide-by-2
1 = Enable reference divide-by-2
Sets reference
divide value (R). Double buffered by register 0.
23:14
R[9:0]
Reference
Divider Mode
0000000000 =
0000000001 =
-----
0 (unused)
1
Maxim Integrated
1111111111 =
1023
17
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